A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used. The CMOS image sensor chip is implemented based on the 0.35μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.